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sy898531l precision differential 3.3v low skew lvpecl 1:9 fanout buffer precision edge is a registered trademark of micrel, inc. micrel inc. ?2180 fortune drive ?san jose, ca 95131 ?usa ?tel +1 ( 408 ) 944-0800 ?fax + 1 (408) 474-1000 ?http://www.micrel.com october 2009 m9999-101509-a hbwhelp@micrel.com or (408) 955-1690 general description the sy898531l is a 3.3v, low skew, 1:9 lvpecl fanout buffer with two selectable clock input pairs. most standard differential input levels can be applied to the clk, /clk pair while lvpecl, cml, or sstl input levels can be applied to the pclk, /pclk pair. to eliminate runt pulses on the outputs during asynchronous assertion/de-assertion of the clock enable pin, the clock enable is synchronized with the input signal. the sy898531l operates from a 3.3v ?% supply and is guaranteed over the full industrial temperature range of 0? to +70?. the sy898531l is part of micrel? high- speed, precision edge product line. datasheets and support documentation can be found on micrel? web site at: www.micrel.com. functional block diagram precision edge features provides nine differential 3.3v lvpecl copies selects between differential clk, /clk or lvpecl clock inputs clk, /clk pair accepts lvds, lvpecl, lvhstl, sstl, hcsl input levels pclk, /pclk pair accepts lvpecl, cml, sstl input levels guaranteed ac performance over temperature and supply voltage: 500mhz maximum output frequency < 2ns propagation delay (in-to-q) < 50ps output skew < 250ps part-to-part skew additive phase jitter, rms: 0.17ps (typical) 3.3v ?% supply voltage 0? to +70? temperature operating range available in a 32-pin tqfp package applications sonet clock distribution backplane distribution markets lan/wan enterprise servers ate test and measurement
micrel, inc. sy898531l october 2009 3 m9999-101509-a hbwhelp@micrel.com or (408) 955-1690 ordering information part number package type operating range package marking lead finish sy898531ltz t32-1 commercial sy898531ltz with pb-free bar-line indicator matte-tin pb-free SY898531LTZTR (2) t32-1 commercial sy898531ltz with pb-free bar-line indicator matte-tin pb-free notes: 1 . contact factory for die availability. dice are guaranteed at t a = 25?, dc electricals only. 2. tape and reel. pin configuration 32-pin tqfp (t32-1)
micrel, inc. sy898531l october 2009 4 m9999-101509-a hbwhelp@micrel.com or (408) 955-1690 pin description pin number pin name pin function 7 v ee ground. 8 clk_en single-ended input: this ttl/cmos input disables and enables the q0- q8 outputs. it is internally connected to a 50k? pull-up resistor and will default to a logic high state if left open. when disabled, q goes low and /q goes high. since clk_en is synchronous with the input clock, the outputs will be enabled/disabled following a rising and a falling edge of the input clock. v th = is approximately 1.5v. 4 clk_sel single-ended input: this single-ended ttl/cmos-compatible input selects the input to the multiplexer. note that this input is internally connected to a 50k? pull-down resistor and will default to logic low state if left open. v th = is approximately 1.5v. 2, 3 clk, /clk differential input: this input pair is a differential signal input to the device. this input accepts ac- or dc-coupled signals. clk is internally connected to a 28k? pull-down resistor and will default to a logic low state if left open while /clk is connected to a 50k? pull-up resistor and will default to a logic high state if left open. this input pair is selected when clk_sel is set to logic low. 5, 6 pclk, /pclk differential input: this input pair is a differential signal input to the device. this input accepts ac- or dc-coupled signals. pclk is internally connected to a 50k? pull-down resistor and will default to a logic low state if left open while /pclk is connected to a 50k? pull-up resistor and will default to a logic high state if left open. this input pair is selected when clk_sel is set to logic high. 1 v cc positive power supply pin: bypass with 0.1f ||0.01 f low esr capacitor as close to the v cc pin as possible. 9, 16, 17, 24, 25, 32 v cco output positive power supply pins: bypass with 0.1 f||0.01f low esr capacitors as close to the v cco pins as possible. 30, 31 28, 29 26, 27 22, 23 20, 21 18, 19 14, 15 12, 13 10, 11 q0, /q0 q1, /q1 q2, /q2 q3, /q3 q4, /q4 q5, /q5 q6, /q6 q7, /q7 q8, /q8 lvpecl differential output pairs: differential buffered output copies of the selected input signal. the output swing is typically 800mv. unused output pairs may be left floating with no impact on jitter. these differential lvpecl outputs are a logic function of the clk, /clk and pclk, /pclk, and clk_sel inputs. see ?ruth table?below. truth table inputs outputs clk_en clk_sel selected source q0 :q8 /q0:/q8 0 0 clk, /clk disabled : low disabled : high 0 1 pclk, /pclk disabled : low disabled : high 1 0 clk, /clk clk /clk 1 1 pclk, /pclk pclk /pclk
micrel, inc. sy898531l october 2009 5 m9999-101509-a hbwhelp@micrel.com or (408) 955-1690 absolute maximum ratings (1) supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?.5v to +4.6v input voltage (v in ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?.5v to v cc +0.5v lvpecl output current (i out ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50ma surge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ma lead temperature (soldering, 20 sec.) . . . . . . . . . . . . . . . . . . . . . . +260? storage temperature (t s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?5? to 150? operating ratings (2) supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.135v to +3.465v ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0? to +70? package thermal resistance (3) tssop ( q ja ) still-air . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50?/w power supply dc electrical characteristics (4) v cc = v cco = 3.3v ?%; t a = 0? to +70?, unless otherwise stated. symbol parameter condition min typ max units v cc power supply 3.135 3.3 3.465 v v cco output power supply 3.135 3.3 3.465 v i ee power supply current no load, max v cc 80 ma lvcmos/lvttl dc electrical characteristics (4) v cc = v cco = 3.3v ?%; t a = 0? to +70?, unless otherwise stated. symbol parameter condition min typ max units v ih input high voltage 2 v cc + 0.3 v v il input low voltage -0.3 0.8 v clk_en v in = v cc = 3.465v 5 a i ih input high current clk_sel v in = v cc = 3.465v 150 a clk_en v in = 0v, v cc = 3.465v -150 a i il input low current clk_sel v in = 0v, v cc = 3.465v -5 a differential dc electrical characteristics (4) v cc = v cco = 3.3v ?%; t a = 0? to +70?, unless otherwise stated. symbol parameter condition min typ max units clk v in = v cc = 3.465v 150 a i ih input high current /clk v in = v cc = 3.465v 5 a clk v in = 0.5v, v cc = 3.465v -5 a i il input low current /clk v in = 0.5v, v cc = 3.465v -150 a v pp peak-to-peak input voltage 0.15 1.3 v v cmr common mode input voltage (5, 6) v ee + 0.5 v cc - 0.85 v notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and func tional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. the data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. q ja value is determined for a 4-layer board in still air unless otherwise stated. 4. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been established. 5. maximum input voltage for clk and /clk is v cc + 0.3v for single ended applications. 6. v ih is defined as the common mode voltage.
micrel, inc. sy898531l october 2009 6 m9999-101509-a hbwhelp@micrel.com or (408) 955-1690 lvpecl dc electrical characteristics (7) v cc = v cco = 3.3v ?%; t a = 0? to +70?, unless otherwise stated. symbol parameter condition min typ max units pclk v in = v cc = 3.465v 150 a i ih input high current /pclk v in = v cc = 3.465v 5 a pclk v in = 0v, v cc = 3.465v -5 a i il input low current /pclk v in = 0v, v cc = 3.465v -150 a v pp peak-to-peak input voltage 0.3 1 v v cmr common mode input voltage (8, 9) v ee + 1.5 v cc v v oh output high voltage (10) v cc - 1.4 v cc ?1.0 v v ol output low voltage (10) v cc ?2.0 v cc - 1.7 v v swing peak-to-peak output voltage swing 0.6 1.0 v notes: 7. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been established. 8. maximum input voltage for pclk and /pclk is v cc + 0.3v for single ended applications. 9. v ih is defined as the common mode voltage. 10. 50? to v cco -2v terminated outputs.
micrel, inc. sy898531l october 2009 7 m9999-101509-a hbwhelp@micrel.com or (408) 955-1690 ac electrical characteristics ( 11 ) v cc = v cco = 3.3v ?%; r l = 50? to v cco -2v; t a = 0? to +70?, unless otherwise stated. symbol parameter condition min typ max units f max maximum operating frequency 500 mhz t pd differential propagation delay clk-to-q, pclk-to-q f 250mhz 1 2 ns output-to-output skew (12) 50 ps t skew part-to-part skew (13) 250 ps t jitter additive phase jitter (14) 155.52mhz, (12khz to 20mhz) 0.17 ps rms t r, t f output rise/fall time 20% to 80% @ 50mhz 300 700 ps odc output duty cycle 48 50 52 % notes: 11. high-frequency ac-parameters are guaranteed by design and characterization. 12. output-to-output skew is measured between two different outputs under identical transitions. 13. part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. this parameter is defined in accordance with jedec standard 65. 14. driving only one input clock.
micrel, inc. sy898531l october 2009 8 m9999-101509-a hbwhelp@micrel.com or (408) 955-1690 timing diagrams figure 1a. clk_en timing diagram figure 1b. propagation delay figure 1c. output-to-output skew
micrel, inc. sy898531l october 2009 9 m9999-101509-a hbwhelp@micrel.com or (408) 955-1690 typical operating characteristics v cc = 3.3v, v ee = 0v, v in = 800mv, r l = 50? to v cc ?v; t a = 25?, unless otherwise stated. output swing vs. frequency 0 100 200 300 400 500 600 700 800 900 0 100 200 300 400 500 600 700 800 900 1000 1100 frequency (mhz) output swing (mv)
micrel, inc. sy898531l october 2009 10 m9999-101509-a hbwhelp@micrel.com or (408) 955-1690 functional characteristics v cc = 3.3v, v ee = 0v, v in = 800mv, r l = 50? to v cc -2v; t a = 25?, unless otherwise stated
micrel, inc. sy898531l october 2009 11 m9999-101509-a hbwhelp@micrel.com or (408) 955-1690 clk, /clk input interface applications figure 2a. lvhstl interface (dc-coupled) figure 2b. lvpecl interface (dc-coupled) figure 2c. lvpecl interface (dc-coupled) figure 2d. lvds interface (dc-coupled) figure 2e. lvpecl interface (ac-coupled)
micrel, inc. sy898531l october 2009 12 m9999-101509-a hbwhelp@micrel.com or (408) 955-1690 pclk, /pclk input interface applications figure 3a. cml open collector interface (dc-coupled) figure 3b. cml built-in pull-up interface (dc-coupled) figure 3c. lvpecl interface (dc-coupled) figure 3d. lvpecl interface (ac-coupled) figure 3e. sstl interface (dc-coupled) figure 3f. lvds interface (ac-coupled)
micrel, inc. sy898531l october 2009 13 m9999-101509-a hbwhelp@micrel.com or (408) 955-1690 package information 32-pin tqfp (t32-1) micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http://www.micrel.com the information furnished by micrel in this data sheet is believed to be accurate and reliable. however, no responsibility is assumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the customer. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. a purchaser? use or sale of micrel products for use in life support appliances, devices or systems is a purchaser? own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ?2009 micrel, incorporated.

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